Topological Design and Dimensioning of Agile All Photonic Networks

TitleTopological Design and Dimensioning of Agile All Photonic Networks
Publication TypeJournal Article
Year of Publication2006
AuthorsMason, L. G., A. Vinokurov, N. Zhao, and D. Plant
JournalJournal of Computer Networks, Special issue on Optical Networking
Volume50
Issue2
Start Page268-287
Date Published02/2006
Abstract

We present the design and analysis of an Agile All-Photonic Network (AAPN); in the context of our study, the agility is derived from sub-microsecond photonic switching and global network synchronization. We have articulated a set of circuit design alternatives in terms of switch configurations referred to as symmetric and asymmetric designs, and 2-layer and 3-layer designs and discuss the implications of these alternatives in terms of transmitter and receiver design and synchronization requirements. In order to evaluate performance and cost of this range of design alternatives, we developed a set of software tools and methodologies for designing and dimensioning our vision of an AAPN. The topological design problem consists of determining the optimal number, size and placement of edge nodes, selector/multiplexers and core switches as well as the placement of the DWDM links so as to minimize network costs while satisfying performance requirements of the supported traffic. A new mixed integer linear programming formulation is presented for core node placement and link connectivity, A methodology has been developed for two-layer and three-layer network topology design and implemented in software. These tools were exercised under a wide variety of equipment cost assumptions for both a metropolitan network and a long-haul network assuming a gravity model for traffic distribution and a flat community of interest factor. Key findings include the determination of near cost optimal designs for both metropolitan (two-layer design) and a Canadian Wide Area Network (WAN, three layer design). We also show the cost and topology sensitivity to the selector switch size and the preferred size in terms of port count and number of switches.

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